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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13705-3E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90595/595G Series
MB90598/F598/F598G/V595/V595G
s DESCRIPTION
The MB90595/595G series with FULL-CAN*1 interface and FLASH ROM is especially designed for automotive and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set of F2MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90595/595G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)) and stepping motor controller. *1: Controller Area Network (CAN) - License of Robert Bosch GmbH *2: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
* Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, VCC of 5.0 V) (Continued)
s PACKAGE
100-pin Plastic QFP
(FPT-100P-M06)
MB90595/595G Series
(Continued) * Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator * Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed: 4-byte instruction queue * Enhanced interrupt function: 8 levels, 34 factors * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS): Up to 10 channels * Embedded ROM size and types Mask ROM: 128 Kbytes Flash ROM: 128 Kbytes Embedded RAM size: 4 Kbytes (MB90V595/595G : 6 Kbytes) * Flash ROM Supports automatic programming, Embedded Algorithm TM* Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector Erase can be performed on each block Block protection with external programming voltage * Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Hardware stand-by mode * Process: 0.5 m CMOS technology * I/O port General-purpose I/O ports: 78 ports Push-pull output and Schmitt trigger input. Programmable on each bit as I/O or signal for peripherals. * Timer Watchdog timer: 1 channel 8/16-bit PPG timer: 8/16-bit x 6 channels 16-bit re-load timer: 2 channels * 16-bit I/O timer Input capture: 4 channels Output compare: 4 channels * Extended I/O serial interface: 1 channel * UART0 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.
2
MB90595/595G Series
* UART1 (SCI) With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized serial transmission (I/O extended transmission) can be selectively used. * Stepping motor controller (4 channels) * External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which is triggered by an external input. * Delayed interrupt generation module: Generates an interrupt request for switching tasks. * 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. * FULL-CAN interface: 1 channel Conforming to Version 2.0 Part A and Part B Flexible message buffering (mailbox and FIFO buffering can be mixed) * 18-bit Time-base counter * External bus interface: Maximum address space 16 Mbytes *: Embedded Algorithm is a trademark of Advanced Micro Devices Inc.
3
MB90595/595G Series
s PRODUCT LINEUP
Features Classification ROM size RAM size Emulator-specific power supply *1 MB90598 Mask ROM product 128 Kbytes 4 Kbytes MB90F598/F598G Flash ROM product 128 Kbytes Boot block Hard-wired reset vector 4 Kbytes MB90V595/V595G Evaluation product None 6 Kbytes None
CPU functions
The number of instructions: 351 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock frequency of 16 MHz) Interrupt processing time: 1.5 s (at machine clock frequency of 16 MHz, minimum value) Clock synchronized transmission (500 K/1 M/2 Mbps) Clock asynchronized transmission (4808/5208/9615/10417/19230/38460/62500 /500000 bps at machine clock frequency of 16 MHz) Transmission can be performed by bi-directional serial transmission or by master/ slave connection. Clock synchronized transmission (62.5 K/125 K/250 K/500 K/1 Mbps) Clock asynchronized transmission (1202/2404/4808/9615/31250 bps) Transmission can be performed by bi-directional serial transmission or by master/ slave connection. Conversion precision: 8/10-bit can be selectively used. Number of inputs: 8 One-shot conversion mode (converts selected channel once only) Scan conversion mode (converts two or more successive channels and can program up to 8 channels) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) Number of channels: 6 (8/16-bit x 6 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: fsys, fsys/21, fsys/22, fsys/23, fsys/24 ( fsys = system clock frequency ) 128s ( fosc = 4MHz : oscillation clock frequency) Number of channels: 2 Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function
UART0
UART1(SCI)
8/10-bit A/D converter
8/16-bit PPG timers (6 channels)
16-bit Reload timer
16-bit I/O timer
16-bit Number of channels: 4 Output compares Pin input factor: A match signal of compare register Input captures Number of channels: 4 Rewriting a register value upon a pin input (rising, falling, or both edges)
(Continued)
4
MB90595/595G Series
(Continued) Features
MB90598
MB90F598/F598G
MB90V595/V595G
CAN Interface
Number of channels: 1 Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID's Supports multiple messages Flexible configuration of acceptance filtering: Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps CAN bit timing setting: MB90xxx:TSEG2 RSJW+2TQ MB90xxxG:TSEG2 RSJW
Stepping motor controller Four high current outputs for each channel (4 channels) Synchronized two 8-bit PWM's for each channel External interrupt circuit Number of inputs: 8 Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. Clock synchronized transmission (31.25 K/62.5 K/125 K/500 K/1 Mbps at system clock frequency of 16 MHz) LSB first/MSB first Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Supports automatic programming, Embedded Algorithm TM and Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Writer from Minato Electronics Inc.
Serial IO
Watchdog timer
Flash Memory
Low-power consumption Sleep/stop/CPU intermittent operation/clock timer/hardware stand-by (stand-by) mode Process Power supply voltage for operation*2 Package QFP-100 CMOS +5 V10 % PGA-256
*1: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used. Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *2: Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.")
5
MB90595/595G Series
s PIN ASSIGNMENT
(Top view)
P16/TIN1 P15/PPG5 P14/PPG4 P13/PPG3 P12/PPG2 P07/OUT3 P06/OUT2 P05/OUT1 P04/OUT0 P03/IN3 P11/PPG1 P10/PPG0 P17/TOT1 P02/IN2 P01/IN1 P00/IN0 Vcc
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
X0
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 Vss P32 P33 P34
P35
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Vss
X1
P95/INT3 P94/INT2 P93/INT1 RST P92/INT0 P91/RX P90/TX DVSS P87/PWM2M3 P86/PWM2P3 P85/PWM1M3 P84/PWM1P3 DVCC P83/PWM2M2 P82/PWM2P2 P81/PWM1M2 P80/PWM1P2 DVSS P77/PWM2M1 P76/PWM2P1 P75/PWM1M1 P74/PWM1P1 DVCC P73/PWM2M0 P72/PWM2P0 P71/PWM1M0 P70/PWM1P0 DVSS HST MD2
P36 P37 P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 Vcc P45/SOT1 P46/SOT2 P47/SCK2 C P50/SIN2 P51/INT4 P52/INT5
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 P57/TOT0
49 MD0
P55/ADTG
AVRH
P60/AN0
P61/AN1
P62/AN2
P63/AN3
Vss
P64/AN4
P54/INT7
P65/AN5
AVRL
AVcc
AVss
P66/AN6
P67/AN7
P53/INT6
(FPT-100P-M06)
6
P56/TIN0
MD1
50
MB90595/595G Series
s PIN DESCRIPTION
Pin no. 82 83 77 52 85 to 88 89 to 92 93 to 98 99 100 1 to 8 9 to 10 12 to 16 17 18 19 20 21 22 24 25 26 Pin name X0 X1 RST HST P00 to P03 IN0 to IN3 P04 to P07 OUT0 to OUT3 P10 to P15 PPG0 to PPG5 P16 TIN1 P17 TOT1 P20 to P27 P30 to P31 P32 to P36 P37 P40 SOT0 P41 SCK0 P42 SIN0 P43 SIN1 P44 SCK1 P45 SOT1 P46 SOT2 P47 SCK2 Circuit type A B C G G D D D G G G D G G G G G G G G Oscillator pin Reset input Hardware standby input General purpose IO Inputs for the Input Captures General purpose IO Outputs for the Output Compares. General purpose IO Outputs for the Programmable Pulse Generators General purpose IO TIN input for the 16-bit Reload Timer 1 General purpose IO TOT output for the 16-bit Reload Timer 1 General purpose IO General purpose IO General purpose IO General purpose IO General purpose IO SOT output for UART 0 General purpose IO SCK input/output for UART 0 General purpose IO SIN input for UART 0 General purpose IO SIN input for UART 1 General purpose IO SCK input/output for UART 1 General purpose IO SOT output for UART 1 General purpose IO SOT output for the Serial IO General purpose IO SCK input/output for the Serial IO Function
(Continued)
7
MB90595/595G Series
Pin no. 28 29 to 32 33 38 to 41 43 to 46 47 48
Pin name P50 SIN2 P51 to P54 INT4 to INT7 P55 ADTG P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P56 TIN0 P57 TOT0 P70 to P73 PWM1P0 PWM1M0 PWM2P0 PWM2M0 P74 to P77 PWM1P1 PWM1M1 PWM2P1 PWM2M1 P80 to P83 PWM1P2 PWM1M2 PWM2P2 PWM2M2 P84 to P87 PWM1P3 PWM1M3 PWM2P3 PWM2M3 P90 TX P91 RX
Circuit type D D D E E D D General purpose IO SIN Input for the Serial IO General purpose IO
Function
External interrupt input for INT4 to INT7 General purpose IO Input for the external trigger of the A/D Converter General purpose IO Inputs for the A/D Converter General purpose IO Inputs for the A/D Converter General purpose IO TIN input for the 16-bit Reload Timer 0 General purpose IO TOT output for the 16-bit Reload Timer 0 General purpose IO
54 to 57
F
Output for Stepper Motor Controller channel 0
General purpose IO F
59 to 62
Output for Stepper Motor Controller channel 1
General purpose IO F
64 to 67
Output for Stepper Motor Controller channel 2
General purpose IO F
69 to 72
Output for Stepper Motor Controller channel 3
74 75
D D
General purpose IO TX output for CAN Interface General purpose IO RX input for CAN Interface
(Continued)
8
MB90595/595G Series
(Continued) Pin no.
76 78 to 80 58, 68 53, 63, 73 34 37 35 36 49, 50 51 27 23, 84 11, 42, 81
Pin name P92 INT0 P93 to P95 INT1 to INT3 DVCC DVSS AVCC AVSS AVRH AVRL MD0 MD1 MD2 C VCC VSS
Circuit type D D Power supply Power supply Power supply Power supply C H Power supply Power supply General purpose IO
Function External interrupt input for INT0 General purpose IO External interrupt input for INT1 to INT3 Dedicated power supply pins for the high current output buffers (Pin No. 54 to 72) Dedicated ground pins for the high current output buffers (Pin No. 54 to 72) Dedicated power supply pin for the A/D Converter Dedicated ground pin for the A/D Converter Upper reference voltage input for the A/D Converter Lower reference voltage input for the A/D Converter Operating mode selection input pins. These pins should be connected to VCC or VSS. Operating mode selection input pin. This pin should be connected to VCC or VSS. External capacitor pin. A capacitor of 0.1F should be connected to this pin and VSS. Power supply pins (5.0 V). Ground pins (0.0 V).
9
MB90595/595G Series
s I/O CIRCUIT TYPE
Circuit Type
X1
Circuit
Remarks * Oscillation feedback resistor: 1 M approx.
X0
A
Standby control signal * Hysteresis input with pull-up Resistor: 50 k approx. B R R HYS * Hysteresis input
C
R
HYS
VCC P-ch
* CMOS output * CMOS Hysteresis input
D
N-ch
R
HYS
VCC P-ch
* CMOS output * CMOS Hysteresis input * Analog input
N-ch
E
Analog input R HYS
(Continued)
10
MB90595/595G Series
Circuit Type
Circuit
VCC P-ch
Remarks * CMOS high current output * CMOS Hysteresis input
High current F
N-ch
R HYS * CMOS output * CMOS Hysteresis input * TTL input (MB90F598/F598G, only in Flash mode)
VCC P-ch
N-ch
G R R
T
HYS
TTL * Hysteresis input Pull-down Resistor: 50 approx. (except MB90F598/F598G)
R H R
HYS
11
MB90595/595G Series
s HANDLING DEVICES
(1) Make Sure that the Voltage not Exceed the Maximum Rating (to Avoid a Latch-up). In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding VCC or an voltage below VSS is applied to input or output pins or a voltage exceeding the rating is applied across VCC and VSS. When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal break-down of devices. To avoid the latch-up, make sure that the voltage not exceed the maximum rating. In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH, DVCC) and analog input voltages not exceed the digital voltage (VCC). (2) Treatment of Unused Pins Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage. Unused input pins should be pulled up or pulled down through at least 2 k resistance. Unused input/output pins may be left open in output state, but if such pins are in input state they should be handled in the same way as input pins. (3) Using external clock In using the external clock, drive X0 pin only and leave X1 pin unconnected. Using external clock X0 MB90595/595G Series Open X1
(4) Power supply pins (Vcc/Vss) In products with multiple Vcc or Vss pins, pins with the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating (See the figure below.) Make sure to connect Vcc and Vss pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between Vcc and Vss pins near the device. Vcc Vss
Vcc Vss Vcc
Vss
MB90595/595G Vcc Series
Vss
Vss
Vcc
12
MB90595/595G Series
(5) Pull-up/down resistors The MB90595 Series does not support internal pull-up/down resistors. Use external components where needed. (6) Crystal Oscillator Circuit Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuit not cross the lines of other circuits. A printed circuit board artwork surrounding the X0 and X1 pins with ground area for stabilizing the operation is highly recommended. (7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). (8) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS. (9) N.C. Pin The N.C. (internally connected) pin must be opened for use. (10) Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V). (11) Indeterminate outputs from ports 0 and 1 During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state. * If RST pin is "H", the outputs become indeterminate. * If RST pin is "L", the outputs become high-impedance. Pay attention to the port output timing shown as follow. RST pin is "H" Oscillation setting time2 Power-on reset1 Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal
Period of indeterminated
*1:Power-on reset time: Period of "clock frequency x 217" (Clock frequency of 16 MHz: 8.19 ms) *2:Oscillation setting time: Period of "clock frequency x 218" (Clock frequency of 16 MHz: 16.38ms) 13
MB90595/595G Series
RST pin is "L" Oscillation setting time2 Power-on reset1 Vcc (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal KB (internal operation clock B) signal PORT (port output) signal High-impedance *1:Power-on reset time: Period of "clock frequency x 217" (Clock frequency of 16 MHz: 8.19 ms) *2:Oscillation setting time: Period of "clock frequency x 218" (Clock frequency of 16 MHz: 16.38ms) (12) Initialization The device contains internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again. (13) Directions of "DIV A, Ri" and "DIVW A, RWi" instructions In the signed multiplication and division instructions ("DIV A, Ri" and "DIVW A, RWi"), the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in "00H". If the values of the corresponding bank register (DTB,ADB,USB,SSB) are set to other than "00H", the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (14) Using REALOS The use of EI2OS is not possible with the REALOS real time operating system.
14
MB90595/595G Series
s BLOCK DIAGRAM
X0,X1 RST HST
Clock Controller
F2MC-16LX CPU
RAM 4 K
16-bit IO Timer 16-bit Input Capture 4 ch IN0 to IN3
ROM/Flash 128 K
16-bit Output Compare 4 ch
OUT0 to OUT3
Prescaler
SOT0 SCK0 SIN0
UART0
8/16-bit PPG 6 ch
PPG0 to PPG5
Prescaler
CAN Controller
RX TX
SOT1 SCK1 SIN1
UART1 (SCI)
16-bit Reload Timer 2 ch
TIN0, TIN1 TOT0, TOT1
F2MC-16 Bus
Prescaler
SOT2 SCK2 SIN2 AVCC AVSS AN0 to AN7 AVRH AVRL ADTG
PWM1M0 to PWM1M3 PWM1P0 to PWM1P3 PWM2M0 to PWM2M3 PWM2P0 to PWM2P3
Serial I/O
SMC 4ch
DVCC0, DVCC1 DVSS0 to DVSS2 10-bit ADC 8 ch External Interrupt 8 ch INT0 to INT7
15
MB90595/595G Series
s MEMORY SPACE
The memory space of the MB90595 Series is shown below
MB90V595/V595G FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) FFFFFFH FF0000H FEFFFFH FE0000H MB90598/F598/F598G ROM (FF bank) ROM (FE bank)
00FFFFH 004000H
ROM (Image of FF bank)
00FFFFH 004000H
ROM (Image of FF bank)
001FFFH 001900H 0018FFH
Peripheral
001FFFH 001900H
Peripheral
RAM 6 K 000100H 0000BFH 000000H Peripheral
0010FFH RAM 4 K 000100H 0000BFH 000000H Peripheral
Memory space map
Note: The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H , the contents of the ROM at FFC000H are accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH.
16
MB90595/595G Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH to 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H Serial Mode Control Register 0 Serial status Register 0 Serial Input/Output Data Register 0 Rate and Data Register 0 Serial Mode Register 1 Serial Control Register 1 Serial Input/Output Data Register 1 Serial Status Register 1 UART1 Prescaler Control Register Analog Input Enable Register Port 0 Direction Register Port 1 Direction Register Port 2 Direction Register Port 3 Direction Register Port 4 Direction Register Port 5 Direction Register Port 6 Direction Register Port 7 Direction Register Port 8 Direction Register Port 9 Direction Register Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Port 7 Data Register Port 8 Data Register Port 9 Data Register Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 Reserved DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 Reserved ADER Reserved UMC0 USR0 UIDR0/ UODR0 URD0 SMR1 SCR1 SIDR1/ SODR1 SSR1 U1CDCR R/W R/W R/W R/W R/W R/W R/W R/W R/W UART1 UART0 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB 0 0 0 0 1 _ 0 0B 0 _ _ _ 1 1 1 1B R/W Port 6, A/D 1 1 1 1 1 1 1 1B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ 0 0 0 0 0 0B Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Peripheral Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB _ _ XXXXXXB
(Continued)
17
MB90595/595G Series
Address 29H to 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH
Register Serial IO Prescaler
Serial Mode Control Register (low-order) Serial Mode Control Register (high-order)
Abbreviation Reserved SCDCR SMCS SMCS SDR SES ENIR EIRR ELVR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PPGC0 PPGC1 PPG01 Reserved PPGC2 PPGC3 PPG23 Reserved PPGC4 PPGC5 PPG45 Reserved PPGC6 PPGC7 PPG67 Reserved PPGC8 PPGC9 PPG89 Reserved
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral
Initial value 0 _ _ _ 1 1 1 1B _ _ _ _ 0 0 0 0B
Serial IO
0 0 0 0 0 0 1 0B XXXXXXXXB _ _ _ _ _ _ _ 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 _ XXB 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B
Serial Data Register Edge Selector External Interrupt Enable Register External Interrupt Request Register External Interrupt Level Register External Interrupt Level Register A/D Control Status Register 0 A/D Control Status Register 1 A/D Data Register 0 A/D Data Register 1
PPG0 Operation Mode Control Register PPG1 Operation Mode Control Register
External Interrupt
A/D Converter
PPG0, 1 Output Pin Control Register
16-bit Programmable Pulse Generator 0/1
PPG2 Operation Mode Control Register PPG3 Operation Mode Control Register
PPG2, 3 Output Pin Control Register
16-bit Programmable Pulse Generator 2/3
PPG4 Operation Mode Control Register PPG5 Operation Mode Control Register
PPG4, 5 Output Pin Control Register
16-bit Programmable Pulse Generator 4/5
PPG6 Operation Mode Control Register PPG7 Operation Mode Control Register
PPG6, 7 Output Pin Control Register
16-bit Programmable Pulse Generator 6/7
PPG8 Operation Mode Control Register PPG9 Operation Mode Control Register
PPG8, 9 Output Pin Control Register
16-bit Programmable Pulse Generator 8/9
(Continued)
18
MB90595/595G Series
Address 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H to 6EH
Register
PPGA Operation Mode Control Register PPGB Operation Mode Control Register
Abbreviation Access PPGCA PPGCB PPGAB Reserved R/W R/W R/W
Peripheral 16-bit Programmable Pulse Generator A/B
Initial value 0 _ 0 0 0 _ _ 1B 0 _ 0 0 0 0 0 1B 0 0 0 0 0 0 _ _B
PPGA, B Output Pin Control Register
Timer Control Status Register 0 Timer Control Status Register 0 Timer 0/Reload Register 0 Timer 0/Reload Register 0 Timer Control Status Register 1 Timer Control Status Register 1 Timer Register 1/Reload Register 1 Timer Register 1/Reload Register 1
Output Compare Control Status Register 0 Output Compare Control Status Register 1 Output Compare Control Status Register 2 Output Compare Control Status Register 3 Input Capture Control Status Register 0/1 Input Capture Control Status Register 2/3
TMCSR0 TMCSR0 TMR0/ TMRLR0 TMR0/ TMRLR0 TMCSR1 TMCSR1 TMR1/ TMRLR1 TMR1/ TMRLR1 OCS0 OCS1 OCS2 OCS3 ICS01 ICS23 PWC0 Reserved
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output Compare 0/1 Output Compare 2/3 16-bit Reload Timer 1 16-bit Reload Timer 0
0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 _ _ 0 0B _ _ _ 0 0 0 0 0B 0 0 0 0 _ _ 0 0B _ _ _ 0 0 0 0 0B
Input Capture 0/1 0 0 0 0 0 0 0 0B Input Capture 2/3 0 0 0 0 0 0 0 0B Stepping Motor Controller 0 Stepping Motor Controller 1 Stepping Motor Controller 2 Stepping Motor Controller 3 0 0 0 0 0 _ _ 0B
PWM Control Register 0
PWM Control Register 1
PWC1 Reserved
R/W
0 0 0 0 0 _ _ 0B
PWM Control Register 2
PWC2 Reserved
R/W
0 0 0 0 0 _ _ 0B
PWM Control Register 3
PWC3 Reserved
R/W
0 0 0 0 0 _ _ 0B
Timer Data Register (low-order) Timer Data Register (high-order) Timer Control Status Register
TCDT TCDT TCCS Reserved
R/W R/W R/W IO Timer
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
(Continued)
19
MB90595/595G Series
Address 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H to 8FH 90H to 9DH 9EH 9FH A0H A1H A2H to A7H A8H A9H AAH to ADH AEH AFH
Register
ROM Mirror Function Selection Register
Abbreviation Access ROMM PWC10 PWC20 PWS10 PWS20 PWC11 PWC21 PWS11 PWS21 PWC12 PWC22 PWS12 PWS22 PWC13 PWC23 PWS13 PWS23 Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral ROM Mirror
Initial value _ _ _ _ _ _ _ 1B XXXXXXXXB XXXXXXXXB _ _ 0 0 0 0 0 0B _ 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB _ _ 0 0 0 0 0 0B _ 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB _ _ 0 0 0 0 0 0B _ 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB _ _ 0 0 0 0 0 0B _ 0 0 0 0 0 0 0B
PWM1 Compare Register 0 PWM2 Compare Register 0 PWM1 Select Register 0 PWM2 Select Register 0 PWM1 Compare Register 1 PWM2 Compare Register 1 PWM1 Select Register 1 PWM2 Select Register 1 PWM1 Compare Register 2 PWM2 Compare Register 2 PWM1 Select Register 2 PWM2 Select Register 2 PWM1 Compare Register 3 PWM2 Compare Register 3 PWM1 Select Register 3 PWM2 Select Register 3
Stepping Motor Controller 0
Stepping Motor Controller 1
Stepping Motor Controller 2
Stepping Motor Controller 3
CAN Controller. Refer to section about CAN Controller Program Address Detection Control Status Register Delayed Interrupt/Request Register Low-Power Mode Control Register Clock Selection Register
PACSR DIRR LPMCR CKSCR Reserved
R/W R/W R/W R/W
Address Match 0 0 0 0 0 0 0 0B Detection Function
Delayed Interrupt _ _ _ _ _ _ _ 0B Low Power Controller Low Power Controller Watchdog Timer 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
Watchdog Timer Control Register Time Base Timer Control Register Flash Memory Control Status Register (MB90F598/F598G only. Otherwise reserved)
WDTC TBTC Reserved FMCS Reserved
R/W R/W
XXXXX 1 1 1B
Time Base Timer 1 _ _ 0 0 1 0 0B
R/W
Flash Memory
0 0 0 X 0 0 0 0B
(Continued)
20
MB90595/595G Series
Address B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to FFH 1900H 1901H 1902H 1903H 1904H 1905H 1906H 1907H 1908H 1909H 190AH 190BH 190CH 190DH 190EH 190FH
Register Interrupt Control Register 00 Interrupt Control Register 01 Interrupt Control Register 02 Interrupt Control Register 03 Interrupt Control Register 04 Interrupt Control Register 05 Interrupt Control Register 06 Interrupt Control Register 07 Interrupt Control Register 08 Interrupt Control Register 09 Interrupt Control Register 10 Interrupt Control Register 11 Interrupt Control Register 12 Interrupt Control Register 13 Interrupt Control Register 14 Interrupt Control Register 15 Reload Register L Reload Register H Reload Register L Reload Register H Reload Register L Reload Register H Reload Register L Reload Register H Reload Register L Reload Register H Reload Register L Reload Register H Reload Register L Reload Register H Reload Register L Reload Register H
Abbreviation Access ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral
Initial value 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B XXXXXXXXB
Interrupt controller
Interrupt controller
Reserved 16-bit Programmable Pulse Generator 0/1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit Programmable Pulse Generator 2/3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit Programmable Pulse Generator 4/5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16-bit Programmable Pulse Generator 6/7 XXXXXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
21
MB90595/595G Series
(Continued) Address
1910H 1911H 1912H 1913H 1914H 1915H 1916H 1917H 1918H to 191FH 1920H 1921H 1922H 1923H 1924H 1925H 1926H 1927H 1928H 1929H 192AH 192BH Input Capture Register 0 (low-order) Input Capture Register 0 (high-order) Input Capture Register 1 (low-order) Input Capture Register 1 (high-order) Input Capture Register 2 (low-order) Input Capture Register 2 (high-order) Input Capture Register 3 (low-order) Input Capture Register 3 (high-order) Output Compare Register 0 (low-order) Output Compare Register 0 (high-order) Output Compare Register 1 (low-order) Output Compare Register 1 (high-order) IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 OCCP0 OCCP0 OCCP1 OCCP1
Register Reload Register L Reload Register H Reload Register L Reload Register H Reload Register L Reload Register H Reload Register L Reload Register H
Abbreviation Access PRLL8 PRLH8 PRLL9 PRLH9 PRLLA PRLHA PRLLB PRLHB R/W R/W R/W R/W R/W R/W R/W R/W Reserved R R
Peripheral 16-bit Programmable Pulse Generator 8/9 16-bit Programmable Pulse Generator A/B 16-bit Programmable Pulse Generator A/B
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
XXXXXXXXB XXXXXXXXB Input Capture 0/1 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Input Capture 2/3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Output Compare 0/1 XXXXXXXXB XXXXXXXXB
R R R R R R R/W R/W R/W R/W
(Continued)
22
MB90595/595G Series
(Continued) Address
192CH 192DH 192EH 192FH 1930H to 19FFH 1A00H to 1AFFH 1B00H to 1BFFH 1C00H to 1EFFH 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H 1FF6H to 1FFFH Program Address Detection Register 0 (low-order) Program Address Detection Register 0 (middle-order) Program Address Detection Register 0 (high-order) Program Address Detection Register 1 (low-order) Program Address Detection Register 1 (middle-order) Program Address Detection Register 1 (high-order) Reserved PADR1 R/W PADR0 R/W
Register Output Compare Register 2 (low-order) Output Compare Register 2 (high-order) Output Compare Register 3 (low-order) Output Compare Register 3 (high-order)
Abbreviation Access OCCP2 OCCP2 OCCP3 OCCP3 R/W R/W
Peripheral
Initial value XXXXXXXXB XXXXXXXXB
Output Compare 2/3 R/W R/W Reserved XXXXXXXXB XXXXXXXXB
CAN Controller. Refer to section about CAN Controller CAN Controller. Refer to section about CAN Controller Reserved XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Address Match Detection Function
Note: Initial value of "_" represents unused bit; "X" represents unknown value. Addresses in the rage 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results in reading "X", and any write access should not be performed.
23
MB90595/595G Series
s CAN CONTROLLER
The CAN controller has the following features: * Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats * Supports transmission of data frames by receiving remote frames * 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration * Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1D acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 Kbit/s to 2 Mbit/s (when input clock is at 16 MHz) List of Control Registers Register Abbreviation Message buffer valid register Transmit request register Transmit cancel register Transmit complete register Receive complete register Remote request receiving register Receive overrun register Receive interrupt enable register Control status register Last event indicator register Receive/transmit error counter Bit timing register BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER CSR LEIR RTEC BTR
Address 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 001B00H 001B01H 001B02H 001B03H 001B04H 001B05H 001B06H 001B07H
Access R/W R/W W R/W R/W R/W R/W R/W R/W, R R/W R R/W
Initial Value 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00---000 0----0-1B -------- 000-0000B 00000000 00000000B -1111111 11111111B
(Continued)
24
MB90595/595G Series
(Continued) Address
001B08H 001B09H 001B0AH 001B0BH 001B0CH 001B0DH 001B0EH 001B0FH 001B10H 001B11H 001B12H 001B13H 001B14H 001B15H 001B16H 001B17H 001B18H 001B19H 001B1AH 001B1BH Acceptance mask register 1 AMR1 R/W XXXXX--- XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB IDE register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register
Register
Abbreviation IDER TRTRR RFWTR TIER
Access R/W R/W R/W R/W
Initial Value XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB
25
MB90595/595G Series
List of Message Buffers (ID Registers) Register Abbreviation Access -R/W
Address
Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXX XXXXXXXXB
001A00H to General-purpose RAM 001A1FH 001A20H 001A21H 001A22H 001A23H 001A24H 001A25H 001A26H 001A27H 001A28H 001A29H 001A2AH 001A2BH 001A2CH 001A2DH 001A2EH 001A2FH 001A30H 001A31H 001A32H 001A33H 001A34H 001A35H 001A36H 001A37H 001A38H 001A39H 001A3AH 001A3BH 001A3CH 001A3DH 001A3EH 001A3FH ID register 7 ID register 6 ID register 5 ID register 4 ID register 3 ID register 2 ID register 1 ID register 0
IDR0
R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
IDR1
R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
IDR2
R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
IDR3
R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
IDR4
R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
IDR5
R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
IDR6
R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
IDR7
R/W XXXXX--- XXXXXXXXB
(Continued)
26
MB90595/595G Series
(Continued) Address
001A40H 001A41H 001A42H 001A43H 001A44H 001A45H 001A46H 001A47H 001A48H 001A49H 001A4AH 001A4BH 001A4CH 001A4DH 001A4EH 001A4FH 001A50H 001A51H 001A52H 001A53H 001A54H 001A55H 001A56H 001A57H 001A58H 001A59H 001A5AH 001A5BH 001A5CH 001A5DH 001A5EH 001A5FH ID register 15 IDR15 R/W XXXXX--- XXXXXXXXB ID register 14 IDR14 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 13 IDR13 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 12 IDR12 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 11 IDR11 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 10 IDR10 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 9 IDR9 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 8 IDR8 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
Register
Abbreviation
Access
Initial Value XXXXXXXX XXXXXXXXB
27
MB90595/595G Series
List of Message Buffers (DLC Registers and Data Registers) Register Abbreviation Access DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address 001A60H 001A61H 001A62H 001A63H 001A64H 001A65H 001A66H 001A67H 001A68H 001A69H 001A6AH 001A6BH 001A6CH 001A6DH 001A6EH 001A6FH 001A70H 001A71H 001A72H 001A73H 001A74H 001A75H 001A76H 001A77H 001A78H 001A79H 001A7AH 001A7BH 001A7CH 001A7DH 001A7EH 001A7FH
Initial Value ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXX ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB XXXXXXXXB to XXXXXXXXB
001A80H to Data register 0 (8 bytes) 001A87H
DTR0
R/W
(Continued)
28
MB90595/595G Series
(Continued)
Address Register Abbreviation DTR1 Access R/W Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB 29
001A88H to Data register 1 (8 bytes) 001A8FH 001A90H to Data register 2 (8 bytes) 001A97H 001A98H to Data register 3 (8 bytes) 001A9FH 001AA0H to Data register 4 (8 bytes) 001AA7H 001AA8H to Data register 5 (8 bytes) 001AAFH 001AB0H to Data register 6 (8 bytes) 001AB7H 001AB8H to Data register 7 (8 bytes) 001ABFH 001AC0H to Data register 8 (8 bytes) 001AC7H 001AC8H to Data register 9 (8 bytes) 001ACFH 001AD0H to Data register 10 (8 bytes) 001AD7H 001AD8H to Data register 11 (8 bytes) 001ADFH 001AE0H to Data register 12 (8 bytes) 001AE7H 001AE8H to Data register 13 (8 bytes) 001AEFH 001AF0H to Data register 14 (8 bytes) 001AF7H 001AF8H to Data register 15 (8 bytes) 001AFFH
DTR2
R/W
DTR3
R/W
DTR4
R/W
DTR5
R/W
DTR6
R/W
DTR7
R/W
DTR8
R/W
DTR9
R/W
DTR10
R/W
DTR11
R/W
DTR12
R/W
DTR13
R/W
DTR14
R/W
DTR15
R/W
MB90595/595G Series
s INTERRUPT MAP
Interrupt source Reset INT9 instruction Exception CAN RX CAN TX/NS External Interrupt (INT0/INT1) Time Base Timer 16-bit Reload Timer 0 8/10-bit A/D Converter I/O Timer External Interrupt (INT2/INT3) Serial I/O External Interrupt (INT4/INT5) Input Capture 0 8/16-bit PPG 0/1 Output Compare 0 8/16-bit PPG 2/3 External Interrupt (INT6/INT7) Input Capture 1 8/16-bit PPG 4/5 Output Compare 1 8/16-bit PPG 6/7 Input Capture 2 8/16-bit PPG 8/9 Output Compare 2 Input Capture 3 8/16-bit PPG A/B Output Compare 3 16-bit Reload Timer 1 UART 0 RX UART 0 TX UART 1 RX UART 1 TX Flash Memory Delayed interrupt 30 EI2OS clear N/A N/A N/A N/A N/A *1 N/A *1 *1 N/A *1 *1 *1 *1 N/A *1 N/A *1 *1 N/A *1 N/A *1 N/A *1 *1 N/A *1 *1 *2 *1 *2 *1 N/A N/A Interrupt vector Number # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 32 # 33 # 34 # 35 # 36 # 37 # 38 # 39 # 40 # 41 # 42 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ---- ---- ---- ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Address ---- ---- ---- 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH
MB90595/595G Series
*1: The interrupt request flag is cleared by the EI2OS interrupt clear signal. *2: The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. N/A:The interrupt request flag is not cleared by the EI2OS interrupt clear signal. Note: * For a peripheral module with two interrupt for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal. * At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number. * If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled.
31
MB90595/595G Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter (VSS = AVSS = 0 V) Rating Symbol Unit Remarks Min. Max. VSS - 0.3 VSS + 6.0 V VCC AVCC VSS - 0.3 VSS + 6.0 V VCC = AVCC *1 AVRH, AVCC AVRH/L, VSS - 0.3 VSS + 6.0 V AVRL AVRH AVRL *1 DVCC VSS - 0.3 VSS + 6.0 V VCC DVCC VI VSS - 0.3 VSS + 6.0 V *2 VO VSS - 0.3 VSS + 6.0 V *2 ICLAMP -2.0 2.0 mA IOL1 -- 15 mA Normal output *3 IOLAV1 -- 4 mA Normal output, average value *4 IOL2 -- 40 mA High current output *3 IOLAV2 -- 30 mA High current output, average value *4 IOL1 -- 100 mA Total normal output IOL2 330 mA Total high current output *5 IOLAV1 -- 50 mA Total normal output, average value Total high current output, average IOLAV2 250 mA value *5 IOH1 -- -15 mA Normal output *3 IOHAV1 -- -4 mA Normal output, average value *4 IOH2 -- -40 mA High current output *3 IOHAV2 -- -30 mA High current output, average value *4 IOH1 -- -100 mA Total normal output IOH2 -- -330 mA Total high current output *5 IOHAV1 -- -50 mA Total normal output, average value Total high current output, average IOHAV2 -- -250 mA value *5 -- 500 mW MB90F598/F598G PD 400 mW MB90598 TA -40 +85 C TSTG -55 +150 C
Power supply voltage
Input voltage Output voltage Clamp Current "L" level max. output current "L" level avg. output current "L" level max. output current "L" level avg. output current "L" level max. overall output current "L" level max. overall output current "L" level avg. overall output current "L" level avg. overall output current "H" level max. output current "H" level avg. output current "H" level max. output current "H" level avg. output current "H" level max. overall output current "H" level max. overall output current "H" level avg. overall output current "H" level avg. overall output current Power consumption Operating temperature Storage temperature
*1: AVCC, AVRL and AVRL does not exceed VCC and AVRL does not exceed AVRH. *2: VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. *3: The maximum output current is a peak value for a corresponding pin. *4: Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5: Total average current is an average current value observed for a 100 ms period for all corresponding pins. Note: Average output current = operating current x operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 32
MB90595/595G Series
2. Recommended Conditions
(VSS = AVSS = 0 V) Parameter Power supply voltage Smooth capacitor Operating temperature Symbol VCC AVCC CS TA Value Min. 4.5 3.0 0.022 -40 Typ. 5.0 0.1 Max. 5.5 5.5 1.0 +85 Unit V V F C Remarks Under normal operation Maintains RAM data in stop mode *
*: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
* C Pin Connection Diagram
C CS
33
MB90595/595G Series
3. DC Characteristics
Parameter Symbol VIHS Input H voltage VIHM VILS Input L voltage VILM Output H voltage Output H voltage Output L voltage Output L voltage Input leak current VOH1 VOH2 VOL1 VOL2 IIL Pin name CMOS hysteresis input pin MD input pin CMOS hysteresis input pin MD input pin Output pins except P70 to P87 P70 to P87 Output pins except P70 to P87 P70 to P87 (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Condition Unit Remarks Min. Typ. Max. -- -- -- -- VCC = 4.5 V, IOH1 = -4.0 mA VCC = 4.5 V, IOH2 = -30.0 mA VCC = 4.5 V, IOL1 = 4.0 mA VCC = 4.5 V, IOL2 = 30.0 mA VCC = 5.5 V, VSS < VI < VCC
VCC = 5.0 V10%, Internal frequency: 16 MHz, At normal operating
0.8 VCC VCC - 0.3 VSS - 0.3 VSS - 0.3 VCC - 0.5 VCC - 0.5 -- -- -5 -- -- --
-- -- -- -- -- 35 50 40
VCC +0.3 VCC +0.3 0.2 VCC VSS +0.3 -- -- 0.4 0.5 5 60 90 60
V V V V V V V V A mA mA mA MB90598 MB90F598
MB90F598G
ICC
VCC = 5.0 V10%, ICCS Power supply current *
Internal frequency:
16 MHz, At sleep VCC VCC = 5.0 V1%,
Internal frequency:
--
11
18
mA
ICTS
2 MHz, At timer mode VCC = 5.0 V10%, At stop, TA = 25C
VCC = 5.0 V10%, At Hardware standby mode, TA = 25C
--
0.3
0.6
mA
ICCH
-- -- --
-- -- 50
20 20 100
A A A MB90598 MB90F598
MB90F598G
ICCH2 Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS, DVCC, DVSS, P70 to P87 P70 to P87
Input capacity
CIN
--
--
5
15
pF
--
--
15
30
pF
*: Current values are tentative and subject to change without notice according to improvements in the characteristics. The power supply current testing conditions are when using the external clock. 34
MB90595/595G Series
4. AC Characteristics
(1) Clock Timing (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Unit Remarks Min. Typ. Max. 3 3 200 62.5 -- 10 -- 1.5 62.5 -- -- -- -- -- -- -- 5 16 333 333 5 -- 5 16 666 MHz When using an oscillation circuit MHz When using an external clock ns ns % ns ns MHz ns Duty ratio is about 30 to 70%. When using external clock
When using an oscillation circuit When using an external clock
Parameter Oscillation frequency Oscillation cycle time Frequency deviation with PLL * Input clock pulse width Input clock rise and fall time Machine clock frequency Machine clock cycle time
Symbol Pin name fC tCYL f PWH, PWL tCR, tCF fCP tCP X0, X1 X0, X1 -- X0 X0 -- --
*: Frequency deviation indicates the maximum frequency difference from the target frequency when using a multiplied clock. f = ----- x 100% fo
+ Central frequency fO -
* Clock Timing tCYL 0.8 VCC X0 PWH tCF Example of Oscillation circuit PWL tCR 0.2 VCC
X0
X1
R
C1
C2
35
MB90595/595G Series
* Guaranteed operation range 5.5 4.5 Power supply voltage VCC (V) 3.0
Guaranteed operation range
Guaranteed PLL operation range
1.5
8 Machine clock fCP (MHz)
16
* External clock frequency and machine clock frequency 16 12 Machine clock fCP (MHz) 9 8 x1/2 (PLL off) x4 x3 x2 x1
4
3
4
8 External clock fC (MHz) *
16
*: When using the oscillation circuit, the maximum oscillation clock frequency is 5 MHz.
AC characteristics are set to the measured reference voltage values below. * Input signal waveform Hysteresis Input Pin
0.8 VCC 0.2 VCC
* Output signal waveform Output Pin
2.4 V 0.8 V
36
MB90595/595G Series
(2) Reset and Hardware Standby Input (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Unit Remarks Min. Max. 16 tCP*1 Reset input time tRSTL RST Oscillation time of oscillator*2 + 16 tCP*1 16 tCP*1 Hardware standby input time tHSTL HST Oscillation time of oscillator*2 + 16 tCP*1 -- -- -- -- ns ms ns ms Under normal operation In stop mode Under normal operation In stop mode
Parameter
Symbol Pin name
*1: "tcp" represents one cycle time of the machine clock. No reset can fully initialize the Flash Memory if it is performing the automatic algorithm. *2: Oscillation time of oscillator is time that the amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillator, the oscillation time is between hundreds of s to several ms. In the external clock, the oscillation time is 0 ms. Under Normal Operation tRSTL, tHSTL RST HST
0.2 VCC
0.2 VCC
In Stop Mode
tRSTL, tHSTL RST HST
0.2VCC
0.2VCC
X0
90% of amplitude
Internal operation clock
16 tCP Oscillation time of
oscillator
Oscillation setting time
Instruction execution Internal reset
37
MB90595/595G Series
(3)Power On Reset
Parameter Power on rise time Power off time
Symbol tR tOFF
Pin name VCC VCC
(VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Condition Unit Remarks Min. Max. -- 0.05 50 30 -- ms ms * Due to repetitive operation
*: VCC must be kept lower than 0.2 V before power-on. Note: * The above values are used for creating a power-on reset. * Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on the power supply using the above values. tR
VCC 0.2 V
2.7 V 0.2 V tOFF
Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock.
0.2 V
VCC 3V
RAM data being held It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
VSS
38
MB90595/595G Series
(4) UART0/1, Serial I/O Timing (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Pin name Condition Unit Remarks Min. Max. SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 Internal clock operSCK0 to SCK2, ation output pins are SIN0 to SIN2 CL = 80 pF + 1 TTL. SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2 SCK0 to SCK2 SCK0 to SCK2, External clock operSOT0 to SOT2 ation output pins are SCK0 to SCK2, CL = 80 pF + 1 TTL. SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 8 tCP -80 100 60 4 tCP 4 tCP -- 60 60 -- 80 -- -- -- -- 150 -- -- ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
Note: 1. AC characteristic in CLK synchronized mode. 2. CL is load capacity value of pins when testing. 3. tCP is the machine cycle (Unit: ns).
* Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.8 V
39
MB90595/595G Series
* External Shift Clock Mode tSLSH SCK 0.2 VCC 0.2 VCC tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC tSHSL 0.8 VCC 0.8 VCC
(5) Timer Input Timing
Parameter Input pulse width
Symbol tTIWH tTIWL
Pin name TIN0, TIN1 IN0 to IN3
(VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Condition Unit Remarks Min. Max. -- 4 tCP -- ns
* Timer Input Timing
0.8 VCC tTIWH
0.8 VCC 0.2 VCC tTIWL 0.2 VCC
40
MB90595/595G Series
(6) Trigger Input Timing (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Condition Unit Remarks Min. Max. -- 5 tCP 1 -- -- ns s Under normal operation In stop mode
Parameter Input pulse width
Symbol tTRGH tTRGL
Pin name INT0 to INT7, ADTG
* Trigger Input Timing
0.8 VCC tTRGH
0.8 VCC 0.2 VCC tTRGL 0.2 VCC
(7) Slew Rate High Current Outputs
Parameter Output Rise/Fall time
Symbol tR2 tF2
Pin name Port P70 to P77, Port P80 to P87
(VCC = 5.0 V10 %, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Condition Unit Remarks Min. Typ. Max. -- 15 40 150 ns
* Slew Rate Output Timing
VH VL VH VL
VH = VOL2 + 0.1 x (VOH2 - VOL2) VL = VOL2 + 0.9 x (VOH2 - VOL2)
tR2
tF2
41
MB90595/595G Series
5. A/D Converter
Parameter Resolution Conversion error Nonlinearity error Differential linearity error Zero transition voltage Full scale transition voltage Conversion time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current (VCC = AVCC = 5.0 V10%, VSS = AVSS = 0 V,3.0 V AVRH - AVRL, TA = -40 C to +85 C) Value Symbol Pin name Remarks Unit Min. Typ. Max. -- -- -- -- VOT VFST -- -- IAIN VAIN -- -- IA IAH -- -- -- -- AN0 to AN7 AN0 to AN7 -- -- AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC -- -- -- --
AVRL - 3.5 AVRH - 6.5
10 -- -- --
AVRL +0.5 AVRH - 1.5
bit LSB LSB LSB mV mV ns ns A V V V mA A A A A LSB *
MB90V595 MB90V595G MB90F598 MB90F598G
5.0 2.5 1.9
AVRL + 4.5 AVRH + 1.5
-- -- -10 AVRL
AVRL + 2.7
352tCP 64tCP -- -- -- -- 5 -- 400 140 -- --
-- -- 10 AVRH AVCC
AVRH - 2.7
0 -- -- -- --
-- 5 600 600 5 4
Reference voltage current
IR
AVRH
MB90598 *
IRH Offset between input channels --
AVRH AN0 to AN7
-- --
*: When not operating A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped.
42
MB90595/595G Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error: The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error 3FF 3FE 3FD Actual conversion value 0.5 LSB
{1 LSB x (N - 1) + 0.5 LSB}
Digital output
004 003 002 001
VNT (measured value) Actual conversion characteristics Theoretical characteristics 0.5 LSB AVRL Analog input AVRH VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB
1 LSB = (Theoretical value)
AVRH - AVRL 1024
[V]
Total error for digital output N =
[LSB]
VOT (Theoretical value) = AVRL + 0.5 LSB[V] VFST (Theoretical value) = AVRH - 1.5 LSB[V]
VNT: Voltage at a transition of digital output from (N - 1) to N
(Continued)
43
MB90595/595G Series
(Continued)
Linearity error 3FF 3FE 3FD Actual conversion value {1 LSB x (N - 1)+ VOT} VFST (measured value) N+1 Actual conversion value Differential linearity error Theoretical characteristics
Digital output
Digital output
N
VNT 004 003 002 001 Theoretical characteristics VOT (measured value) AVRL Analog input AVRH Actual conversion characteristics
N-1
V(N + 1)T (measured value) VNT (measured value)
N-2
Actual conversion value
AVRL
Analog input
AVRH
VNT - {1 LSB x (N - 1) + VOT} Linearity error of [LSB] digital output N = 1 LSB Differential linearity error = of digital N 1 LSB = VFST - VOT V(N + 1)T - VNT 1 LSB - 1 LSB [LSB]
[V] 1022 VOT: Voltage at transition of digital output from "000H" to "001H" VFST: Voltage at transition of digital output from "3FEH" to "3FFH"
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions, : * Output impedance values of the external circuit of 15 k or lower are recommended. * When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz). * Equipment of analog input circuit model
Analog input Comparator 3.2 k Max. 30 pF Max.
* Error The smaller the | AVRH - AVRL |, the greater the error would become relatively. 44
MB90595/595G Series
s ORDERING INFORMATION
Part number MB90598PF MB90F598PF MB90F598GPF MB90V595CR MB90V595GCR Package 100-pin Plastic QFP (FPT-100P-M06) 256-pin Ceramic PGA (PGA-256C-A01) For evaluation Remarks
45
MB90595/595G Series
s PACKAGE DIMENSION
100-pin plastic QFP (FPT-100P-M06) Note: This package dimension is for the reference. Please consult separately about a formal version.
23.900.40(.941.016) 20.000.20(.787.008)
80 81 51 50
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX Details of "B" part
0
10
0.800.20 (.031.008)
C
2000 FUJITSU LIMITED F100008-3C-3
Dimensions in mm (inches)
46
MB90595/595G Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0101 (c) FUJITSU LIMITED Printed in Japan

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